Introduction

This is the tool for customer to calculate proper register settings for Aptina sensors/SOCs. The User only needs to specify input clock frequency (EXTCLK), desired output clock frequency (PIXCLK), and frame rate requirements. The Register Wizard will calculate and generate a list of register settings for users.
As shown in Figure 1, the sensor clock will be calculated based on frame rate requirements. Based on sensor clock frequency and required pixel clock, the SOC clock frequency is calculated. The SOC clock frequency should be as low as possible to provide the lowest power consumption, but still maintain continuous data flow from sensor to the output interface. An Rx/Tx FIFO with programmable watermarks allows for the continuous flow of data.

Supported Sensors

Note that newer Aptina Sensor/SOCs use the new version of Register Wizard. If the following screens do not match those of the Register Wizard you're running, please reference the new Register Wizard documentation to determine if that applies to your sensor:
Register Wizard User Guide 2.pdf

Figure 1. Regsiter Wizard PLL calculation GUI.

Figure 2 Register Wizard Timing calculation GUI.

Figure 3. Register Wizard calculated Register List.