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Demo3 has several new features over Demo2X (no longer being shipped):

• The PC interface is upgraded from USB2 to USB3. The raw bandwidth is 5Gb for USB3.
• Demo3 can do power cycle on headboard.
• Demo3 can be remotely upgraded on FPGA binary.
• Demo3 can display sensor video directly on HDMI monitor.
• Demo3 takes serial interface (CCP, quad MIPI/HiSpi) from headboard directly.

Thru-put Rates

The slowest of any of the below items will be your limiting factor, please consider the USB connection is variable based on the PC it is plugged into, how many apps are running, how much hardware is connected, etc. (basically you need cycles from the CPU).  The more things enabled in the DevWare colorpipe or plugins being used will reduce the rate at which frames are requested which also slows you down.

• Demo3
  • Front End
    • Serial Data – 800 Mbps/lane
      • 4 lanes = ~3.2 Gbps
      • 1 lane = 800 Mbps
    • Parallel Data – 150 MHz @ 16 bits = 2.4 Gbps
      • 10-16 bits – use 16 bits as your multiplier
      • 8 bits – can do 2 pixels per clock
    • Frame Buffer Demo Board – 4.8 Gbps
  • Back end
    • USB3
      • Typically around 2.1 – 2.3 Gbps on a good system with not too much running

Demo3 Architecture

The Demo3 Baseboard contains three major chips: FPGA, HDMI transmitter, and FPGA frame buffer memory. Below shows the block diagram of Demo3 Baseboard. The blocks are explained in further detail in the following sections.

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We are using Altera EP2AGX45DF25C4N FPGA on this card. For more detailed FPGA architecture and functional spec/register map please refer to Demo3 Baseboard FPGA Specification document. The FPGA has the following interfaces: 

• Headboard serial image data interface: MIPI/HiSpi/CCP is the differential serial interface to the FPGA. FPGA will de-serialize the serial image data into parallel data inside FPGA for further processing.

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• SDRAM: There is one Micron MT41J64M16JT-15E DDR3 SDRAM talking to FPGA. The size is 1Gbits and the interface is running at 375 MHz. (1Gbits  $12, 2Gbits $30)
• SPI flash memory: FX3 and FPGA share the same SPI flash memory. The flash memory stores both FPGA binary and FX3 application codes. There is an external SPI interface switch controlled by FX3 to decide which device to access the flash. The behavior of the switch is detailed below.

• By default FX3gets to talk to flash.
• Altera Byteblaster can program the flash no matter where the switch is set to.
• FX3 boots up and loads applications from SPI flash memory. After FX3 done with the SPI flash, FX3 flips the switch for FPGA to take SPI bus. FX3 then toggles GPIO52 (NCONFIG of FPGA) from LOW to HIGH for FPGA to start getting binary from SPI flash. FPGA binary has to be stored from address 0x0 of the flash, and the binary will take about half of the size of the flash. So FX3 applications will need to stay at the bottom half of the flash, and FX3 has to be able to load codes from wherever the code is stored.

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Demo3 headboard connector is different from the Demo2X one. An adapter board is needed in order for Demo3 to work with legacy headboard. The different adapter boards are explained in Demo3 Configurations page.