Demo3

Owned by John Medalen
Last updated: Apr 03, 2024 by John Medalen
5 min read

Overview

The Demo3 baseboard sends sensor image data to the host computer through a high-bandwidth USB3 interface as well as to external HDMI monitor. It takes single/dual/quad MIPI interface, dual/quad lanes HiSpi interface, CCP, and parallel interface from sensor headboard. The board has 1G Bit memory for frame buffer before sending image data to host computer.

Demo3 has several new features over Demo2X (no longer being shipped):

  • The PC interface is upgraded from USB2 to USB3. The raw bandwidth is 5Gb for USB3.
  • Demo3 can do power cycle on headboard.
  • Demo3 can be remotely upgraded on FPGA binary.
  • Demo3 can display sensor video directly on HDMI monitor.
  • Demo3 takes serial interface (CCP, quad MIPI/HiSpi) from headboard directly.

Thru-put Rates

The slowest of any of the below items will be your limiting factor, please consider the USB connection is variable based on the PC it is plugged into, how many apps are running, how much hardware is connected, etc. (basically you need cycles from the CPU).  The more things enabled in the DevWare colorpipe or plugins being used will reduce the rate at which frames are requested which also slows you down.

  • Demo3
    • Front End
      • Serial Data – 800 Mbps/lane
        • 4 lanes = ~3.2 Gbps
        • 1 lane = 800 Mbps
      • Parallel Data – 150 MHz @ 16 bits = 2.4 Gbps
        • 10-16 bits – use 16 bits as your multiplier
        • 8 bits – can do 2 pixels per clock
      • Frame Buffer Demo Board – 4.8 Gbps
    • Back end
      • USB3
        • Typically around 2.1 – 2.3 Gbps on a good system with not too much running

Demo3 Architecture

The Demo3 Baseboard contains three major chips: FPGA, HDMI transmitter, and FPGA frame buffer memory. Below shows the block diagram of Demo3 Baseboard. The blocks are explained in further detail in the following sections.

FPGA

We are using Altera EP2AGX45DF25C4N FPGA on this card. For more detailed FPGA architecture and functional spec/register map please refer to Demo3 Baseboard FPGA Specification document. The FPGA has the following interfaces:


  • Headboard serial image data interface: MIPI/HiSpi/CCP is the differential serial interface to the FPGA. FPGA will de-serialize the serial image data into parallel data inside FPGA for further processing.
  • Headboard parallel image data interface: FPGA takes parallel image data from sensor headboard. It consists of up to 16 bits data bus, Line_Valid, Frame_Valid, and pixel clock. The maximum speed for the interface is 96 MHz.
  • Memory interface: FPGA external memory is served as frame buffer for the image data. There is one bank of DRAM interface for this. The interface configuration is 64M x 16 bit and is connecting to 1 physical Micron DDR3 SDRAM chips. The interface is running at 333 MHz.
  • I2C interface: I2C comes from FX3. The I2C device address for FPGA register is 0x64. The FPGA uses two separate smart slave module to repeat I2C to HDMI transmitter and headboard.

  • HDMI transmitter interface:The 36-bit data bus is configured either in 16-bit YCbCr or 24-bit RGB. Data with clock, and HSYNC, VSYNC are sent to HDMI transmitter. The signal level is CMOS 1.8V. The clock speed is either 74.25 MHz or 148.5 MHz, depending on the video format.
  • FX3 parallel data interface:FPGA sends parallel image data to FX3 through 32-bit wide data interface. It consists of up to 32 bits data bus, controlling signals, and pixel clock. The maximum speed for the interface is 100 MHz.

Cypress FX3

Cypress FX3 is the EZ-USB controller and is the interface to host PC. It has the following interfaces

  • I2C interface: FX3 is the I2C master to the whole demo system. Host PC send command through USB3 to FX3 and FX3 send out the command to the system through I2C.
  • FPGA interface: It is a 32-bit parallel single data rate interface with other control signals and clock. It runs at 100 MHz to provide 3.2 Gbit bandwidth. FPGA sends image data to FX3 through this interface.
  • USB3 interface: It is a bi-directional, 5Gb/s raw bandwidth serial interface to host PC. FX3 sends image data to host PC through USB3. FX3 also gets commands from host PC through USB3.

The FX3 has an ARM9 processor, which runs firmware to control the FPGA, and communicate with the USB host. The FX3 firmware is available in different flavors and is explained in detail in Flex Config page.

HDMI transmitter

The Demo3 uses Analog Devices ADV7511 for HDMI transmitter. It supports HDMI 1.4 standard with 12-bit Deep Color. The digital video input supports both RGB and YCbCr. This block has the following interfaces

  • I2C interface: I2C bus to access registers inside ADC7511. The I2C device address is 0x72.
  • Digital video data input: The interface includes 36-bit data bus, data clock, HSYNC and VSYNC. It is configured as either 16-bit YCbCr or 24-bit RGB video data input.
  • HDMI output: This interface includes 3 differential pair data and 1 differential pair clock to HDMI connector. It is running at 10x the pixel clock rates.
  • Audio input: This interface is not used.

Memory

  • SDRAM: There is one Micron MT41J64M16JT-15E DDR3 SDRAM talking to FPGA. The size is 1Gbits and the interface is running at 375 MHz. (1Gbits  $12, 2Gbits $30)
  • SPI flash memory: FX3 and FPGA share the same SPI flash memory. The flash memory stores both FPGA binary and FX3 application codes. There is an external SPI interface switch controlled by FX3 to decide which device to access the flash. The behavior of the switch is detailed below.



  • By default FX3gets to talk to flash.
  • Altera Byteblaster can program the flash no matter where the switch is set to.
  • FX3 boots up and loads applications from SPI flash memory. After FX3 done with the SPI flash, FX3 flips the switch for FPGA to take SPI bus. FX3 then toggles GPIO52 (NCONFIG of FPGA) from LOW to HIGH for FPGA to start getting binary from SPI flash. FPGA binary has to be stored from address 0x0 of the flash, and the binary will take about half of the size of the flash. So FX3 applications will need to stay at the bottom half of the flash, and FX3 has to be able to load codes from wherever the code is stored.

Clock, Power and Reset

The main power input to the Demo3 Baseboard is DC 5V. It comes from USB3 with the ability of 900mA supply current. None of the chips in this board require any kind of sequencing.

There is no reset to FX3. The only way to reset FX3 is power cycle the board. i.e. unplug and then plug in USB3 cable. FX3 has GPIO26 to reset FPGA, and FPGA will relay the reset to reset the headboard.

There are two clock sources for FPGA. One for HDMI video interface and the other for parallel image data interface and DDR2 SDRAM interface. FPGA uses the 27 MHz source to generate 148.5 MHz clock for HDMI transmitter interface. FPGA uses the 48 MHz source to generate 100 MHz for FX3 parallel data interface and 375 MHz DDR3 SDRAM interface clock.

Configuration

Demo3 headboard connector is different from the Demo2X one. An adapter board is needed in order for Demo3 to work with legacy headboard. The different adapter boards are explained in Demo3 Configurations page.


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