Page Comparison

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• SP3 controls the 20-bit-to-10-bit mux on the AP010x REV2 headboards. DevWare sets it to 0 on startup.  
• SP3 is GSHT_CTL on many others. DevWare sets it to 0 on startup for all except ASX340/343/350 or AP010x.
• SP4 is TRIGGER on many headboards. DevWare sets it to 0 on startup for all except ASX340/343/350 or AP010x.
• SP5 is FRAMESYNC on ASX340/343/350. DevWare sets it to 0 on startup.
• SP5 is SHUTDOWN on many other sensors. This can be controlled with midlib mode MI_SENSOR_SHUTDOWN.
  • On Demo3 only, DevWare sets SP5 to high-Z on startup for all except ASX340/344/350 or AP010x. 
• SP7 controls the 20-bit-to-10-bit mux on the AP010x REV1 headboards. DevWare sets it to 0 on startup.

The actual registers and bitfields can be found in the board_data folder;

Demo2X; \Aptina Imaging\board_data\Demo2x_FPGA_C1.cdat - see "SP_CONTROL"

Demo3;   \Aptina Imaging\board_data\Demo3_5551.cdat - see "SensorGPIOControl".