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Data Path

Streaming video data passes through the Demo2X. The data path consists of a Cypress USB chip (FX2), a 500K gate FPGA and 64MB of SDRAM. There are two programmable memories, one is an EEPROM that contains the code for the USB chip's firmware and the other is a Xilinx memory chip holding the FPGA code. Both of these memories need to be burned-in after manufacturing or for updating. Updating can be done via the USB from the PC using the Hardware Update Tool which is installed with DevSuite. As can be seen from the timing diagram, below, both of these memories are both loaded, simultaneously, during the first second after power-up.

Frame Flow Control

The SDRAM is used to buffer video frames as they are sent by the USB controller. With 64MB of memory, the Demo2X can store 3 frames (triple-buffer) of up to a 10MP sensor at 16 bits-per-pixel. The FPGA uses the Line_Valid (LV), Frame_Valid (FV) and Pixel_Clock (PCLK) along with the USB controllers SLSC lines to optimize the data flow through the USB. It is designed to prevent data overflow. Complete frames are guaranteed even for large sensors.

Data Path and Frame Flow Control Diagram

I2C

Demo2X is an I2C master. The I2C bus goes through the headboard interface and to the sensor and headboard EEPROM. I2C is used to load sensor registers. Some serial boards have an FPGA that is also connected to the I2C bus.

Power and I2C Routing

Many factors make it necessary to sequence the powering up of the Demo2X and the connected headboard. Demo2X allows time for all of its parts to be loaded and be stable before the 5V USB power is connected to the headboard. This takes about 1 second.

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